Integrated circuits, such as those used in semiconductor devices, require input/output (I/O) terminals to couple to an external bus or interface with external circuitry. For example, memory devices, such as dynamic random access memory (DRAM) devices, synchronous dynamic random access memory (SDRAM), reduced latency dynamic random access memory (RLDRAM), and others, transfer data from an array of memory cells to an output terminal, such as a DQ pad. Data may then be placed on a transmission line having a termination to properly transfer data to receiving circuitry external to the memory device, such as a processor or memory controller. In order for the memory device to successful transfer data, the memory device conventionally includes an output driver that is capable of driving data onto the transmission line at drive capabilities required by the external bus or circuitry. Output drivers commonly include a pull-up device, mainly comprising of PMOS transistors, and a pull-down device, comprising of NMOS transistors. The term “pull-up” refers to the device being adapted to pull an output node to a desired logic high voltage level “1”, and the term “pull-down” refers to the device being adapted to pull the output node to a desired logic low voltage level “0”. The output driver compensates for variations in supply voltage to provide more consistent switching speed characteristics between the logic high and low output signals. Additionally, the transistors in the output driver may be designed to adjust impedances in the respective pull-up and pull-down devices to control the output impedance of the output driver.
FIG. 1 is an example of a prior art complementary metal oxide semiconductor (CMOS) output driver circuit 10 having both a pull-up circuit 11 and a pull-down circuit 12. The pull-up circuit 11 and pull-down circuit 12 are coupled in series with each other between supply voltages VCC and VSS, and also coupled to a DQ pad for outputting a DQ signal at an output node 50. The pull-up circuit 11 includes a PMOS output transistor 22 coupled to an active low input PUPF at an input node 20. The input node 20 is further coupled to a PMOS enabling transistor 26 that is coupled in series with a diode-connected PMOS transistor 24. The drains of the transistors 22, 24 are coupled to the output node 50. The drain of the diode-connected transistor 24 is additionally coupled to its gate.
The pull-down device 12 is configured in a similar manner as the pull-up transistor 11, except that each of the PMOS transistors 22, 26, 24 are replaced by NMOS transistors 32, 36, 34 respectively, and are coupled to VSS instead of VCC. An active high input signal PDN may be received at a node 30. As explained in greater detail below, the PUPF and PDN signals may be driven to place the DQ pad at a high logic level, a low logic level, or a tristate (high impedance) level.
In operation, to drive the DQ pad high, the PUPF signal is low, and the PDN signal is also low, thus disabling the pull-down circuit 12. The low PUPF signal received by the gate of the transistor 22 at node 20 turns ON the transistor 22, thereby pulls the voltage at the output node 50 towards the supply voltage VCC. The gate of the transistor 26 also receives the low PUPF signal, and assuming the DQ voltage is initially low, both the transistor 26 and the diode-connected transistor 24 are turned ON to pull the DQ pad towards VCC. The DQ pad will be pulled towards VCC by both devices until it reaches a voltage level that is greater than VCC less the threshold voltage of the diode-connected transistor 24 and subsequently turn OFF the transistor 24.
To drive the DQ pad low, the PUPF signal transitions high to disable the pull-up circuit 11, and the PDN signal also transitions high. The high PDN signal turns ON the transistors 32, 36, and therefore couples the node 50 to VSS through the transistor 32. At the same time, since the voltage of the DQ pad is initially high due to the previous operation of the pull-up circuit 11, the diode-connected transistor 34 is initially turned ON to drain the node 50 towards VSS through the transistor 36. When the DQ pad is pulled down to the threshold voltage of the diode-connected transistor 34, the transistor 34 is disabled, and the DQ pad is pulled down to VSS solely through the transistor 32.
To drive the DQ pad to a tristate condition, the PUPF signal is driven inactive high to disable the pull-up circuit 11, and the PDN signal is driven inactive low to disable the pull-down circuit 12. The PUPF signal should never be active low at the same time that the PDN signal is active high or else the pull-up circuit 11 and the pull-down circuit 12 will both be active and they will couple VCC to VSS.
A constant resistance at the output node is conventionally desired for matching the output impedance of the output driver circuit 10 to the external impedance. For example, during the operation of the pull-up circuit 11, the output resistance at the node 50 may be held substantially constant by increasing the current from the DQ pad at a rate that is proportional to the change in the voltage at the DQ pad as the DQ pad charges towards the logic high level. Therefore, the constant output resistance may be met by establishing a linear relationship between the total current and the voltage at the node 50. However, the I-V relationship of the transistors 22, 32 deviate from a linear relationship as the transistors 22, 32 approach saturation because the current through the transistors 22, 32 no longer continues to change as the voltage at the drains of the transistors 22, 32 change. The drain-to-source impedances of the transistors 22, 32 then begin to increase. For this reason, the pull-up circuit 11 uses an extra current path formed by the transistors 24, 26, and the pull-down circuit 12 uses an extra current path formed by the transistors 34, 36. The manner in which these extra current paths make the output impedance more constant will now be explained with reference to FIG. 2.
FIG. 2 is a signal diagram 201 that shows at the lower half of FIG. 2 a first graph 214 of the current through the transistor 32 as a function of voltage at node 50. It can be seen that the current is initially directly proportional to voltage, but deviates from a linear relationship as the transistor 32 becomes saturated. Also shown at the lower half of FIG. 2 is a graph 215 of the current through the transistors 34, 36. Although the transistor 36 is driven with the same PDN signal that drives the transistor 32, the presence of the diode-connected transistor 34 causes the saturation of the transistor 36 to be well beyond the voltage at the DQ pad that causes saturation of the transistor 32. The total current from the DQ pad, i.e., the sum of the current through the first path formed by the transistor 32 and the current through the second path formed by the transistors 34, 36, is shown as the graph 212 at the top of FIG. 2. As shown by the graph 212, the current from the output driver circuit 10 is much more linear compared to the graph 214 showing the current from the transistor 32 alone. The second path formed by the transistors 34, 36 therefore makes the output impedance of the output driver circuit 10 substantially more linear. However, as further shown by the graph 210 in FIG. 2, the output impedance still changes excessively. Graph 210 is a linear curve showing what the current-voltage characteristics would be if the output impedance of the driver circuit 10 were constant, i.e., the current was directly proportional to voltage. The graphs show the actual current deviating from a linear response as the voltage of the DQ pad increases towards VCC. This deviation is the result of the diode-connected transistor 34 being unable to provide enough current at higher voltages. Consequently, the output impedance changes as the voltage at the DQ pad approaches the supply voltages VCC and VSS.
Changes to the output resistance may cause impedance mismatches between the output driver circuit 10 and transmission lines, and therefore cause the voltage at the DQ pad to become more susceptible to reflection and noise resulting in misinterpreted voltage levels by receiving external circuitry. Furthermore, due to a reduction in current at higher voltages, the size of the transistors 22, 26, 24, 32, 36, 34 may be made larger to reduce the resistance and thereby increase the current. However, with larger transistors the output current deviates from the ideal linear response (indicated by the graph 210 in FIG. 2) sooner at low and mid voltage ranges. Additionally, larger transistors consume more space on the chip, and increase the circuit size that is already large due to the bulky diode-connected transistors. Larger transistors are particularly undesirable in memory devices that require multiple DQ pads, such as an RLDRAM device that conventionally includes at least 36 DQ pads.
There is, therefore, a need in the art for a smaller sized linear output driver that reduces the size of its transistors while still achieving current linearity over a wider range of voltages.